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Document Reference No.: FT_000198
MORPH-IC-II Datasheet
Version 1.04
Clearance No.: FTDI# 164
Morph-IC II Pin-out
J1
(Top View)
Fixed Voltage
Lines
Variable Voltage
Lines
Morph-IC II Pin-out
J2
(Top View)
VCCUSB
AD4
AD6
TXE#
WR#
GND
IOK1
IOP11
3V3IO
IOT4
IOR3
GND
IOL4
IOP4
3V3IO
IOP5
IOR7
GND
NC
IOL9
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VCCSW
AD5
AD7
RXF#
RD#
GND
RESETIN#
IOC1
3V3IO
IOT7
IOL3
GND
IOM4
IOK4
3V3IO
IOK5
ION8
GND
IOR8
IOM11
AD3
AD0
NC
IOE4
IOE5
GND
IOA7
IOA3
3V3IO
IOA5
IOA6
GND
IOG7
IOG6
V_BANK4
IOD5
IOE6
GND
IOF9
IOC12
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
AD2
AD1
NC
IOE3
IOD4
GND
CLKIN
GND
3V3IO
IOD6
IOB7
GND
IOA9
IOF6
V_BANK4
IOC5
IOD8
GND
IOC11
IOC13
Fig. 4 – Pin outs of J1 & J2
# = Active Low
The signal names of J1 and J2 are illustrated in Fig. 4. The pins are colour coded to indicate whether or
not the pin is associated with I/O BANK4. Likewise Fig. 5 defines the pins associated with the variable
voltage level tolerant I/O BANK4. Fig 5 also details labelling of J3 and J4 signals.
Copyright ? 2010 Future Technology Devices International Limited
12
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